add, addu, sub, subu, mult, div, mfhi, mflo, mfcz, lwcz, slt, jr, and, or, xor, nor
ISTRUZIONI DI TIPO I
addi, addiu, andi, ori, slti, lw, lh, lhu, lb, lbu, sw, sh, sb, lui, swcz, beq, bne
{lw, lh, lhu, lb, lbu, sw, sh, sb, lui, swcz} => [lw/sw]
ISTRUZIONI DI TIPO J
j, jal
CICLO 1.ISTRUCTION FETCH
•IR <- M[PC] : MemRead , IRWrite, IorD = 0;
•PC <- PC +4 : ALuSrcA = 0, ALUSrcB = 01, ALUOp = 00, PCSource = 00, PCWrite;
CICLO 2.ISTRUCTION DECODE / REGISTER FETCH
ALUSrcA = 0, ALUSrcB = 11, ALUOp = 00;
CICLO 3.EXECUTE
• lw/sw :
ALUSrcA = 1, ALUSrcB = 10, ALUOp = 00;
• addi, addiu, slti
ALUSrcA = 1, ALUSrcB = 10, ALUOp = 10;
• add, addu, sub, subu, mult, div, and, or, xor, nor, mfhi, mflo, mfcz, lwcz, jr :
ALUSrcA = 1, ALUSrcB = 00, ALUOp = 10;
• beq, bne :
ALUSrcA = 1, ALUSrcB = 00, ALUOp = 01, PCWriteCond, PCSource = 01.
CICLO 4.
• memory access (sw)
IorD = 1, MemWrite;
• memory access (lw)
IorD = 1, MemRead;
• R-Type completion {add, addu, sub, subu, mult, div, and, or, xor, nor, mfhi, mflo, mfcz, lwcz, jr}:
MemtoReg = 0, RegDst = 1, RegWrite;
• addi, addiu, slti :
MemtoReg = 0, RegDst = 0, RegWrite;
CICLO 5. WRITE BACK STEP
• lw
MemtoReg = 1, RegDest = 0, RegWrite.